3D MEMS architecture for routing signals through hermetically sealed MEMS sensor to top and bottom interconnects
Enables wafer-scale bonding of MEMS and IC
IC technology agnostic (CMOS, GaAs, SiGe, etc)
IC wafer I/O is accessible through the MEMS 3DTCVs
Enables full wafer-scale testing of MEMS + IC
MEMS/CMOS wafers can be diced to produce self-packaged SoC (System on Chip) dies that can be bump bonded directly to a PC Board. This means no additional packaging or bond wires and significant packaging cost savings.
3DTCV enables wafer-scale bonding of MEMS IMU and IC